1. Field of the Invention
The present invention relates to a charged particle lithography system, and to methods for exposing a wafer.
2. Description of the Related Art
A design for an integrated circuit is typically represented in a computer-readable file. The GDS-II file format (GDS stands for Graphic Data Signal) is a database file format which is the lithography industry standard for data exchange of integrated circuit or IC layout artwork. For lithography machines which use masks, a GDS-II file is typically used to manufacture a mask or set of masks which are then used by the lithography machine. For maskless lithography machines, the GDS-II file is electronically processed to put it into a format suitable for controlling the lithography machine. For charged particle lithography machines, the GDS-II file is converted into a set of control signals for controlling the charged particles beams used in the lithography process.
A preprocessing unit may be used to process the GDS-II file to generate intermediate data for the present lithography system. Depending on the architecture option this intermediate data is either a bitmap format or a description of areas in vector format. The Present lithography system uses the intermediate data to write patterns on to a wafer using a large quantity of electron beams.
The architecture of the data path needs to be defined to implement all features required to be able to scale up to a full-field high volume at the lowest cost. The data path features required for the full-field high volume machine contains different types of correction, which are required for tool calibrations and process variations.
In yet another aspect, the invention provides a method for exposing a wafer according to pattern data using a charged particle lithography machine generating a plurality of charged particle beamlets for exposing the wafer. The method comprises providing the pattern data in a vector format, rendering the vector pattern data to generate multi-level pattern data, dithering the multi-level pattern data to generate two-level pattern data, supplying the two-level pattern data to the charged particle lithography machine, and switching on and off the beamlets generated by the charged particle lithography machine on the basis of the two-level pattern data, wherein the pattern data is adjusted on the basis of corrective data.
Adjusting the pattern data may comprise adjusting the vector pattern data on the basis of first corrective data, adjusting the multi-level pattern data on the basis of second corrective data, and/or adjusting the two-level pattern data on the basis of third corrective data.
Rendering the vector pattern data may comprise defining an array of pixel cells, and assigning multi-level values to the pixel cells based on relative coverage of the pixel cells by features defined by the vector pattern data. Dithering the multi-level pattern data may comprise forming the two-level pattern data by application of error diffusion on the multi-level pattern data. The error diffusion may comprise distributing quantization error in a pixel of the multi-level pattern data to one or more adjacent pixels of the multi-level pattern data. Application of error diffusion may include defining an array of pixels, dividing the array of pixels into portions, each portion being assigned to be exposed by a different beamlet, determining error diffusion parameter values for each portion, and assigning a two-level value to the pixels within each portion using error diffusion parameter values. The error diffusion parameter values may comprise a threshold value and a weight value for the higher level of the two-level value. The error diffusion parameter values may further comprise a weight value for the lower level of the two-level value. The threshold value may be equal to 50% of the high level pixel value.
The threshold value equals the average of the high level pixel value and the low level pixel value. Determining the error diffusion parameter values may be based on beamlet current measurements. The error diffusion parameter value may be a threshold value, and assigning a two-level value to the pixel cells within a portion may be based on comparison with the threshold value determined for the portion. The error diffusion parameter may be a value representing the higher level of the two-level value, and it may be a one-dimensional error diffusion or a two-dimensional error diffusion. The application of error diffusion may be restricted by disallowing diffusion towards one or more pixels with a multi-level value equal to or below a further threshold value, and the further threshold value may be equal to zero.
The application of error diffusion may be restricted by disallowing diffusion to one or more pixels that are located outside the features described in the vector pattern data.
The first corrective data may comprise a proximity effect correction, which may comprise a dose correction, a shape correction, or a combination of dose correction and shape correction. The first corrective data may comprise a resist heating correction, a correction to compensate for variation in the position of one or more of the beamlets, a correction to compensate for errors in the positioning of a field of the wafer with respect to the wafer, and/or a correction to compensate for errors in the size of a field of the wafer.
The correction may comprise an adjustment of the vector pattern data that results in shifting the multi-level pattern data by less than a full pixel. The wafer may be moved in a mechanical scan direction during exposure of the wafer, and the correction may comprise an adjustment of the vector pattern data that results a shift of the multi-level pattern data having a component in both the mechanical scan direction and a direction substantially perpendicular to the mechanical scan direction. The first corrective data may comprise a correction to compensate for variation in the transmission time of the beamlet control signals to the lithography machine.
The method may comprise switching the beamlets on and off by beamlet blanker electrodes in a beamlet blanker array, each beamlet blanker electrode receiving a beamlet control signal, wherein the first corrective data comprises a correction to compensate for a difference in the time when beamlet control signals are received by the beamlet blanker electrodes. The beamlets may be deflected to scan the surface of the wafer, and the first corrective data may comprise a correction to compensate for variations in the amount of deflection experienced by different beamlets.
Dithering the multi-level pattern data may comprise assigning a high value or a low value for each corresponding multi-level value of the multi-level pattern data based on comparison with a threshold value, and a quantization error may be calculated by subtracting a weight of the high level value or a weight of the low level value from the multi-level pattern data, the weight of the high level value being defined on the basis of the second corrective data. The weight of the low value may be defined on the basis of the second corrective data. The threshold value may be defined on the basis of the second corrective data. Dithering the multi-level pattern data may comprise determining a two-level value by comparing a corresponding multi-level value of the multi-level pattern data to a threshold value, and wherein adjusting the pattern data comprises adjusting the threshold value on the basis of the second corrective data.
The second corrective data may comprise a correction to compensate for variation in the position of one or more beamlets, a correction to compensate for errors in the positioning of a field of the wafer with respect to the wafer, and/or a correction to compensate for errors in the size of a field of the wafer. The correction may comprise an adjustment of the multi-level pattern data equivalent to shifting the multi-level pattern data by less than a full pixel.
The wafer may be moved in a mechanical scan direction during exposure of the wafer, and the correction may comprise an adjustment of the multi-level pattern data that results a shift having a component in both the mechanical scan direction and a direction substantially perpendicular to the mechanical scan direction. The second corrective data may comprise a correction for realizing a soft edge between areas exposed by different beamlets or groups of beamlets. The soft edge may be made by multiplying the multi-level pattern data with a soft edge factor, the soft edge factor increasing linearly with the distance to the edge until a maximum value is reached. The maximum value may be 1, a starting value of the factor may be 0 at an edge, and the soft edge may have a width of about 0.5 to 1.5 micron.
The third corrective data may comprise a correction to compensate for variation in the position of one or more beamlets, a correction to compensate for errors in the positioning of a field of the wafer with respect to the wafer, and/or a correction to compensate for errors in the size of a field of the wafer. The wafer may be moved in a mechanical scan direction during exposure of the wafer, and the third corrective data may comprise a full pixel shift in the mechanical scan direction. The wafer may be moved in a mechanical scan direction during exposure of the wafer, and the third corrective data may comprise a full pixel shift in a direction substantially perpendicular to the mechanical scan direction.
The step of providing pattern data in a vector format may comprise providing design data describing a plurality of layers of a device design, and transforming a layer of the design data to generate two dimensional pattern data in vector format. The design data may comprise data in a GDS-II format or an OASIS format. The vector pattern data may comprise vector data describing the shape of features for patterning on the wafer and dose values associated with the features. The vector pattern data may comprise vector data describing the shape of features for patterning on the wafer and an array of dose values for corresponding areas on the wafer.
The multi-level pattern data may comprise an array of multi-level values assigned to pixel cells, and the multi-level pattern data may comprise gray scale bitmap data. The two-level pattern data may comprise black/white bitmap data.
The rendering and rasterizing steps may be performed by off-line processing whereby the rendering and rasterizing of pattern data for the whole wafer is completed before the wafer scan begins. The rendering and rasterizing steps may be performed once per design. The rendering and rasterizing steps may be performed by in-line processing, whereby the rendering and rasterizing of pattern data for a first set of fields of the wafer is completed before a scan of the first set of fields begins, while the rendering and rasterizing of pattern data for the remaining fields of the wafer continues during the scan of the first set of fields. The first set of fields and the remaining fields may be such that they do not overlap. The first set of fields and the remaining fields together may comprise the complete area of the wafer to be exposed.
The first set of fields may be exposed in a first scan of the wafer and the remaining fields exposed in a second scan of the wafer. A first subset of the beamlets may be allocated for exposing the first set of fields and a second subset of the beamlets may be allocated for exposing the remaining fields. The rendering and rasterizing steps may be performed once per wafer, and may be performed by real-time processing, whereby the rendering and rasterizing for a first set of fields of the wafer continues during the scan of the first set of fields. The rendering and rasterizing steps may be performed once per field of the wafer, and may be performed during exposure of the wafer.
In a further aspect of the invention, a charged particle lithography system for exposing a wafer according to pattern data is provided. The system comprises an electron optical column for generating a plurality of electron beamlets for exposing the wafer, the electron optical column including a beamlet blanker array for switching the beamlets on or off, a data path for transmitting beamlet control data for control of the switching of the beamlets, and a wafer positioning system for moving the wafer under the electron optical column in an x-direction. The wafer positioning system is provided with synchronization signals from the data path to align the wafer with the electron beams from the electron-optical column. The data path further comprises one or more processing units for generating the beamlet control data and one or more transmission channels for transmitting the beamlet control data to the beamlet blanker array.
The transmission system may comprise a plurality of transmission channels, each transmission channel for transmitting data for a corresponding group of beamlets. The beamlets may be arranged in a plurality of groups, each transmission channel for transmitting beamlet control data for one of the groups of beamlets. The data path may comprise a plurality of multiplexers, each multiplexer for multiplexing beamlet control data for a group of beamlets. The system may further comprise a plurality of demultiplexers, each demultiplexer for demultiplexing beamlet control data for a group of beamlets. The data path may comprise electrical-to-optical conversion devices for converting the beamlet control data generated by the processing units to an optical signal for transmission to the charged particle lithography machine.
The transmission channels may comprise optical fibers for guiding the optical signal, and the beamlet blanker array may comprise optical-to-electrical conversion devices for receiving the optical signal and converting it to an electrical signal for control of the beamlets. The transmission system may comprise an array of lenses and a mirror, the array of lenses for guiding the optical signal onto the mirror, and the mirror for reflecting the optical signal onto the beamlet blanker array of the charged particle lithography machine.
The system may further comprise a first number of processing units sufficient for processing the pattern data to generate first beamlet control data for a first subset of the beamlets allocated for exposing a first portion of the wafer. The system may further comprise a cross-connect switch for connecting the processing units to a subset of the transmission channels.
The beamlets may be arranged in a plurality of groups, each processing unit for generating beamlet control data for any one group of beamlets, and each transmission channel dedicated for transmitting beamlet control data for one of the groups of beamlets. Seven processing units may be provided for every twelve transmission channels.
The charged particle lithography system may have a first subset of the beamlets allocated for exposing a first portion of the wafer and a second subset of the beamlets for exposing a second portion of the wafer, and the cross-connect switch may connect the processing units to a first subset of the transmission channels corresponding to the first subset of the beamlets for a scan of the first portion of the wafer, and connect the processing units to a second subset of the transmission channels corresponding to the second subset of the beamlets for a scan of the second portion of the wafer. The first number of processing units may be sufficient for processing the pattern data to generate the first beamlet control data and processing the pattern data to generate the second beamlet control data, but not sufficient for processing the pattern data to generate both the first and second beamlet control data at the same time.
The lithography system may be adapted for exposing the wafer in a dual-pass scan in which a first portion of the wafer is exposed according to first pattern data and subsequently a second portion of the wafer is exposed according to second pattern data, and the processing units may comprise memory, the memory being divided into a first memory portion for storing the first pattern data and a second memory portion for storing the second pattern data, and during exposure of the second portion of a wafer of a current batch of wafers, first pattern data for a wafer of a next batch of wafers may be loaded into the first memory portion.
In another aspect the invention comprises a method for exposing a wafer in a charged particle lithography system. The method comprises generating a plurality of charged particle beamlets, the beamlets arranged in groups, each group comprising an array of beamlets, moving the wafer under the beamlets in a first direction at a wafer scan speed, deflecting the beamlets in a second direction substantially perpendicular to the first direction at a deflection scan speed, and adjusting the wafer scan speed to adjust a dose imparted by the beamlets on the wafer. The beamlets may expose the wafer using a parallel projection writing strategy, and the deflection scan speed may comprise a beamlet scan speed and a fly-back speed.
Each array of beamlets may have a projection pitch Pproj in the first direction between beamlets of the array, and a group distance equal to the projection pitch Pproj multiplied by the number of beamlets in the array, and wherein a scan step, equal to the relative movement in the x-direction between the beamlets and the wafer between each scan, equals the group distance divided by an integer K. The scan step may be adjusted by adjusting a beamlet scan speed and/or a fly-back speed, or by adjusting a beamlet deflection period, the beamlet deflection period comprising the time for one beamlet scan in the y-direction and a beamlet fly-back time. The deflection period may be equal to the group distance divided by integer K, divided by the beamlet scan speed. The method may be such that K satisfies a requirement that the greatest common denominator of K and the number of beamlets in each array, is one.
In yet another aspect the invention relates to a method for exposing a wafer in a charged particle lithography system. The method comprises generating a plurality of charged particle beamlets, the beamlets arranged in groups, each group comprising an array of beamlets, moving the wafer under the beamlets in an first direction at a wafer scan speed, deflecting the beamlets in a second direction substantially perpendicular to the first direction at a deflection scan speed, switching the beamlets on and off according to pattern data as the beamlets are deflected to expose pixels onto the wafer, and adjusting the wafer scan speed relative to the deflection scan speed to adjust the pixel width in the first direction.
The beamlets may expose the wafer using a parallel projection writing strategy, and the deflection scan speed comprises a beamlet scan speed and a fly-back speed. Each array of beamlets may have a projection pitch Pproj in the first direction between beamlets of the array, and a group distance equal to the projection pitch Pproj multiplied by the number of beamlets in the array, and a scan step, may be equal to the relative movement in the x-direction between the beamlets and the wafer between each scan, equals the group distance divided by an integer K. The scan step may be adjusted by adjusting a beamlet scan speed and/or a fly-back speed. The scan step may be adjusted by adjusting a beamlet deflection period, the beamlet deflection period comprising the time for one beamlet scan in the y-direction and a beamlet fly-back time. The deflection period may be equal to the group distance divided by integer K, divided by the beamlet scan speed. The method may be such that K satisfies a requirement that the greatest common denominator of K and the number of beamlets in each array, is one.
In yet another aspect, the invention provides a method for exposing a wafer in a charged particle lithography system. The method comprises generating a plurality of charged particle beamlets, the beamlets arranged in groups, each group comprising an array of beamlets, creating relative movement in a first direction between the beamlets and the wafer, deflecting the beamlets in a second direction substantially perpendicular to the x-direction at a deflection scan speed, so that each beamlet exposes a plurality of scan lines on the wafer, and adjusting the relative movement in the first direction and the deflection of the beamlets in the second direction to adjust a dose imparted by the beamlets on the wafer. Each array of beamlets has a projection pitch Pproj in the first direction between beamlets of the array, and a group distance equal to the projection pitch Pproj multiplied by the number of beamlets in the array, and the relative movement in the x-direction between the beamlets and the wafer between each scan equals the group distance divided by an integer K.
The value K may be selected so that the greatest common denominator of K and the number of beamlets in each array, is one. A width of the scan lines may be the projection pitch Pproj divided by integer K. The beamlets may be switched on and off according to pattern data as the beamlets are deflected to expose pixels onto the wafer, and a width of the pixels in the first direction may be the projection pitch Pproj divided by integer K.
In yet a further aspect, the invention relates to a method for defining features for writing on a target using a lithography process. The method comprises defining an array of cells, the features occupying one or more of the cells, and describing for each cell any corners of the features that fall within the cell. The corner may be described by a corner position, a first vector, and a second vector, the two vectors originating from the position. The corner positions may be described by two coordinates, and/or by Cartesian coordinates. Each vector may be described by an orientation code specifying a direction for the vector.
The feature may be defined as the area bounded by the vectors and the cell boundaries when moving in a predetermined direction from the first vector to the second vector, such as a clockwise direction. A pseudo corner may be defined for a feature falling partly within a cell but otherwise having no corners within the cell. The pseudo corner may be described by first and second vectors oriented at 180 degrees with respect to each other.
The vectors may be selected to only have a direction parallel to a cell boundary or perpendicular to a cell boundary, and/or to only have a direction parallel to a cell boundary, perpendicular to a cell boundary, or at 45 degrees to a cell boundary.
A minimum feature pitch may be defined and the cells may have a size equal to or less than the minimum feature pitch. The cells may have a size equal to or less than half of the square root of two multiplied by the minimum feature pitch. The minimum feature pitch may be defined as a size equal to or greater than the size of the cells multiplied by the square root of two.
For features or part of features having an edge oriented at 45 degrees to a cell boundary, a minimum feature pitch may be defined having a size equal to or greater than the size of the cells multiplied by the square root of two. A maximum number of corners may be defined for each cell. Each cell may contain one or more features, and/or a portion of one of more features. Each cell may comprise pattern data for part of a field of the wafer, or pattern data of a stripe of a field of the wafer.
In another aspect, the invention comprises a method of processing pattern data for use in a lithography process, the method comprising providing the pattern data in a vector format, transforming the vector pattern data a generate pattern data in a cell based format, and rasterizing the cell based pattern data to generate two-level pattern data for use in the lithography process. The cell based pattern data may comprise cell data describing features occupying one or more of the cells of an array of cells, the cell data describing for each cell any corners of the features that fall within the cell. Rasterizing the cell based pattern data may be performed in real-time processing while the lithography process is being performed. Rasterizing the cell based pattern data may comprise rendering the cell based pattern data to generate multi-level pattern data, and dithering the multi-level pattern data to generate the two-level pattern data.
In yet another aspect, the invention provides a method for exposing a wafer according to pattern data using a charged particle lithography machine generating a plurality of charged particle beamlets for exposing the wafer, the method comprising providing the pattern data in a vector format, transforming the vector pattern data a generate pattern data in a cell based format, rasterizing the cell based pattern data to generate two-level pattern data, streaming the two-level pattern data to a beamlet blanker array for switching on and off the beamlets generated by the charged particle lithography machine, and switching on and off the beamlets on the basis of the two-level pattern data.
The cell based pattern data may comprise cell data describing features occupying one or more of the cells of an array of cells, the cell data describing for each cell any corners of the features that fall within the cell. Rasterizing the cell based pattern data may be performed in real-time processing while the lithography machine is exposing the wafer. Rasterizing the cell based pattern data may comprise rendering the cell based pattern data to generate multi-level pattern data, and dithering the multi-level pattern data to generate the two-level pattern data.